A nonvolatile memory device (hereinafter, referred to as an NVM device) including a plurality of nonvolatile memory chips (hereinafter, referred to as an NVM chip) has been known as a semiconductor memory device including a plurality of semiconductor memory portion.
Recently, a demand for large capacity storage systems, using NVM devices (for example, flash memory devices) featuring a low cost and high-density packaging, has been increasing. A larger number of NVM chips are required for implementing a larger capacity storage system.
A larger number of NVM chips coupled to a memory controller directly relates to a larger number of signal lines for the NVM chips. Examples of the signal line for the NVM chip include a data system signal line, a chip enable (CE) signal line, and a ready/busy (R/B) signal line. A data system signal is transmitted on the data system signal line. The data system signal includes a command, an address, a write enable (WE), read enable (RE), command latch enable (CLE), address latch enable (ALE), and I/O data (write (program) or read target data). A chip enable (CE) signal for selecting a NVM chip is transmitted on the CE signal line. A ready busy (R/B) signal indicating an operation state of an NVM chip is transmitted on the R/B signal line.
The increase in the number of signal lines for the NVM chip involves at least one of the following problems.    (1) The number of pins of the memory controller increases. This results in an increased size of the memory controller, which might result in an increased cost of the memory controller.    (2) The signal lines occupy a large package occupying area. This results in an increased size of the NVM device (for example, a substrate).    (3) The packaging density of the signal lines increases to render the packaging more difficult. This results in an increased packaging steps and an increased packaging cost.
Thus, the number of signal lines between the plurality of NVM chips and the memory controller is preferably reduced. PTL 1 discloses a technique for achieving a smaller number of signal lines. PTL 1 discloses the following configuration: “a memory system includes a NAND memory incorporating a plurality of chips and a NAND controller 112 that controls the NAND memory. A bus switch is provided that switches the connection of the signal lines between a plurality of chips incorporated in the NAND controller 112 and the NAND memory. Thus, the load capacity of the signal line at the time of accessing the NAND memory 10 can be reduced, whereby a signal delay can be prevented”.